Today, in order to boost electrical performances of CMOS devices at reduced power consumption, there is a desire to co-integrate high mobility channels such as Ge or SixGe1−x and III-V semiconductors on the same Silicon substrate, so as to obtain a high-speed Si-based CMOS having a high electron mobility characteristic of the Group III-V semiconductor and a high hole mobility characteristic of Ge or SixGe1−x.
U.S. Pat. No. 8,987,141 refers to a method of manufacturing a Si-based high-mobility Group III-V/Ge channel CMOS device. The resulting device has nMOS and pMOS devices side by side, i.e. in horizontal direction.
In L. Czornomaz et al., “Confined Epitaxial Lateral Overgrowth (CELO): A Novel Concept for Scalable Integration of CMOS-compatible InGaAs-on-insulator MOSFETs on Large-Area Si Substrates”, 2015 Symposium on VLSI Technology Digest of Technical Papers, pp. T172-T173, the authors refer to a CMOS-compatible integration of high-quality InGaAs on insulator (InGaAs-OI) on Si substrates. The starting point is to define a seed area to the Si substrate in a thermal oxide, from which the InGaAs material will grow. Unlike classical epitaxial lateral overgrowth, the growth is geometrically constrained in a cavity that is defined by a sacrificial layer. The final InGaAs geometry, thickness and roughness are hence defined by the morphology of the sacrificial layer rather than by lithography or chemical mechanical polishing. The shape of the cavity implies that defect filtering occurs at the seed region of the structure due to an abrupt change of the growth direction from vertical to lateral. Propagating defects are therefore blocked in 2D.